SN74S225

16

× 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

WITH 3-STATE OUTPUTS

SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998

5

POST OFFICE BOX 655303

recommended operating conditions

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.75

5

5.25

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

IOH

High level output current

Q outputs

–6.5

mA

IOH

High-level output current

All other outputs

–3.2

mA

IOL

Low level output current

Q outputs

16

mA

IOL

Low-level output current

All other outputs

8

mA

TA

Operating free-air temperature

0

70

°C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIK

VCC = 4.75 V,

II = –18 mA

–1.2

V

VOH

Q outputs

VCC = 4.75 V,

IOL = –6.5 mA

2.4

2.9

V

VOH

All others

VCC = 4.75 V,

IOL = –3.2 mA

2.4

2.9

V

VOL

Q outputs

VCC = 4.75 V,

IOL = 16 mA

0.35

0.5

V

VOL

All others

VCC = 4.75 V,

IOL = 8 mA

0.35

0.5

V

IOZH

VCC = 5.25 V,

VO = 2.4 V

50

µA

IOZL

VCC = 5.25 V,

VO = 0.5 V

–50

µA

II

VCC = 5.25 V,

VI = 5.5 V

1

mA

IIH

Data

VCC = 5 25 V

VI =2 7V

40

µA

IIH

All others

VCC = 5.25 V,

VI = 2.7 V

25

µA

IIL

Data

VCC = 5 25 V

VI =0 5V

–1

mA

IIL

All others

VCC = 5.25 V,

VI = 0.5 V

–0.25

mA

IOS‡

VCC = 5.25 V,

VO = 0

–30

–100

mA

ICC§

VCC = 5.25 V

80

120

mA

† All typical values are at VCC = 5 V, TA = 25°C.

‡ Duration of the short circuit should not exceed one second.

§ ICC is measured with all inputs grounded and the outputs open.

timing requirements over recommended operating conditions (unless otherwise noted) (see

Figure 1)

MIN

NOM

MAX

UNIT

fclock

Clock frequency

10

MHz

CLKA or CLKB high

25

tw

Pulse duration

UNCK IN low

7

ns

CLR low

40

t

Set p time before CLKA

↑ or CLKB↑

Data (see Note 3)

–20

ns

tsu

Setup time before CLKA

↑ or CLKB↑

CLR inactive

25

ns

th

Hold time after CLKA

↑ or CLKB↑

70

ns

NOTE 3: Data must be set up within 20 ns after the load-clock positive transition.