SN54LVTH18646A, SN54LVTH182646A, SN74LVTH18646A, SN74LVTH182646A

3.3-V ABT SCAN TEST DEVICES

WITH 18-BIT TRANSCEIVERS AND REGISTERS

SCBS311D – MARCH 1994 – REVISED JUNE 1997

1

POST OFFICE BOX 655303

SCOPE

™ Family of Testability Products

Widebus

™ Family

Mixed-Mode Signal Operation (5-V Input

Down to 2.7 V

Circuitry to Provide Multiplexed

Transmission of Stored and Real-Time Data

Need for External Pullup/Pulldown

Resistors

Have Equivalent 25-

Ω Series Resistors, So

No External Resistors Are Required

(JTAG) Test Access Port and

Boundary-Scan Architecture

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

(PM) Packages Using 0.5-mm

Center-to-Center Spacings and 68-Pin

Ceramic Quad Flat (HV) Packages Using

25-mil Center-to-Center Spacings

description

The ’LVTH18646A and ’LVTH182646A scan test devices with 18-bit bus transceivers and registers are

members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices

supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan

access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed

transmission of data directly from the input bus or from the internal registers. They can be used either as two

9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot

samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating

the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers

and registers.

Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the

transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR

is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating

both buses.

Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is

clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data

is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for

presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB

and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed

with the ’LVTH18646A and ’LVTH182646A.

Copyright

© 1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and Widebus are trademarks of Texas Instruments Incorporated.