SN74SSTVF16857

14BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES411B – AUGUST 2002 – REVISED APRIL 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

The device supports low-power standby operation. When RESET is low, the differential input receivers are

RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input always must

be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in

the low state during power up.

FUNCTION TABLE

INPUTS

OUTPUT

RESET

CLK

CLK

D

OUTPUT

Q

H

↑

↓

H

H

H

↑↓

LL

H

L or H

L or H

X

Q0

L

X, or floating

X, or floating

X, or floating

L

logic diagram (positive logic)

1D

C1

R

To 13 Other Channels

34

1

RESET

Q1

39

CLK

38

CLK

35

VREF

48

D1

One of 14 Channels