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LM97937RMET Datasheet(PDF) 6 Page - Texas Instruments |
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LM97937RMET Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 80 page  VA3.3 OVRB/ TRIGGER VA1.8 VA1.8 AGND OVRA/ TRIGRDY VA1.8 VA3.3 80: 80: AGND S+ S- VA3.3 AGND VA3.3 SYNC+ 50: 50: SYNC- 1k: 2.5V AGND 2k: 2k: 34k: 34k: 3pF 1k: 2.5V LM97937 SNVS990A – DECEMBER 2013 – REVISED JANUARY 2014 www.ti.com PIN NAME TYPE/DIAGRAM DESCRIPTION Differential SYNCb signal input pins. DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100 Ω differential termination is provided therefore an external 27, 28 SYNCb+, SYNCb– termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common- mode range. The SYNCb signal is active low and is therefore asserted when the voltage at SYNCb+ is less than at SYNCb–. Differential high speed serial data lane pins for channel A. These pins must be AC coupled to the receiving device. The differential trace 38, 39, 36, 37 SA0+, SA0–, SA1+, SA1– routing from these pins must maintain a 100 Ω characteristic impedance. In single- lane mode, SA0 +/– is utilized to transfer data and SA1+/– is undefined and may be left floating. Differential high speed serial data lane pins for channel B. These pins must be AC coupled to the receiving device. The differential trace routing from these pins 32, 33, 34, 35 SB0+, SB0–, SB1+, SB1– must maintain a 100 Ω characteristic impedance. In single-lane mode, SB0+/– is utilized to transfer data and SB1+/– is undefined and may be left floating. Dual purpose pin. While in SNRBoost mode, this pin outputs the channel A over-range signal. While in Bit-Burst mode and in Trigger sub- 44 OVRA/ TRIGRDY mode, this pin outputs the “trigger ready” signal that indicates when a Bit-Burst cycle has completed and a new trigger edge may be applied. This pin is a 1.8 V CMOS logic level output. Dual purpose pin. While in SNRBoost mode, this pin outputs the channel B over-range signal. In this mode, the pin is a 1.8 V CMOS logic level output. 43 OVRB/ TRIGGER While in Bit-Burst mode and Trigger sub- mode, this pin is the “trigger” signal that is used to start a new Bit-Burst cycle when a rising edge is applied. In this mode, the pin is a 1.8 V CMOS logic level asynchronous input. 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: LM97937 |
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