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SN74LVC125ARGYRG4 Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LVC125ARGYRG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 28 page 2A 2Y 2OE 1A 1Y 1OE 4A 4Y 4OE 3A 3Y 3OE SN74LVC125A www.ti.com SCAS290Q – JANUARY 1993 – REVISED JANUARY 2015 9 Detailed Description 9.1 Overview The SN74LVC125A device is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. 9.2 Functional Block Diagram 9.3 Feature Description • Wide operating voltage range – Operates from 1.65 V to 5.5 V • Allows down voltage translation • Inputs accept voltages to 5.5 V 9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUT Y OE A L H H L L L H X Z Copyright © 1993–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC125A |
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