4

MC68EZ328 Product Brief

System Configuration

2

System Integration Module

The MC68EZ328 system integration module (SIM28-EZ) consists of several functions that control the

system start-up, initialization, configuration, and the external bus with a minimum of external devices. The

memory interface allows the user to interface gluelessly with the widely available SRAM and EPROM as

well as FLASH memory. With the assistance of chip-select logic, wait states can be programmable. The

interrupt controller accepts and resolves the priority from internal modules and external generated

interrupts. It also handles the masking and wake-up selection control for power control. The low-power

logic can be used to control the CPU power dissipation by altering the frequency or stopping the CPU. In

addition, the SIM28-EZ is capable of configuring the pin to allow the user to select either dedicated I/O or

parallel I/O. This feature help to increase the number of available I/O ports by reclaiming when the

dedicated function is not used.

2.1

System Configuration

The MC68EZ328 system configuration logic consists of a system control register (SCR) which allows the

user to configure operation of the following major functions:

•

System Status and Control Logic

•

Bus Error Generation Control

•

Protect module control registers from access by user programs

2.2

VCO/PLL Clock Synthesizer

The clock synthesizer can operate with either an external crystal or an external oscillator for reference,

using the internal phase-locked loop (PLL) and voltage-controlled oscillator (VCO), or an external clock

can directly drive the clock signal at the operating frequency.

2.3

Chip Select Logic

The MC68EZ328 provides eight programmable general purpose chip-select signals. For a given chip-

select block, the user may choose whether the chip-select allows read-only, or both read and write

accesses, whether a DTACK is automatically generated for this chip-select, and after how many wait states

(from zero to six) the DTACK will be generated.

2.4

External Bus Interface

The external bus interface handles the transfer of information between the internal 68EC000 core and the

memory, peripherals, or other processing elements in the external address space. It consists of a 16 bit

68000 bus interface for internal and a 8 bit interface to outside.

2.5

Interrupt Controller

The interrupt controller accepts and prioritizes both internal and external interrupt requests and generates a

vector number during the CPU interrupt acknowledge cycle. Interrupt nesting is also provided so that an