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ISPLSI2032E-135LT48 Datasheet(PDF) 2 Page - Lattice Semiconductor |
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ISPLSI2032E-135LT48 Datasheet(HTML) 2 Page - Lattice Semiconductor |
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2 / 14 page  Specifications ispLSI 2032E 2 Functional Block Diagram Figure 1. ispLSI 2032E Functional Block Diagram Global Routing Pool (GRP) A0 A1 A3 A7 A6 A5 A4 A2 GOE 0 Notes: *Y1 and RESET are multiplexed on the same pin I/O 0 I/O 1 I/O 2 I/O 3 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 TDI/IN 0 TDO/IN 1 I/O 4 I/O 5 Y0 Y1* TCK/Y2 BSCAN TMS 0139/2032E programmed to be a combinatorial input, output or bi- directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compat- ible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive (48-pin device only). Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032E device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2032E device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2032E are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. |
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