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CY62128L-70ZC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY62128L-70ZC
Description  128K x 8 Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62128L-70ZC Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY62128
3
PRELIMINARY
Capacitance[5]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
9
pF
COUT
Output Capacitance
9
pF
AC Test Loads and Waveforms
Switching Characteristics[3,6] Over the Operating Range
62128–55
62128–70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
55
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
5
5
ns
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
20
35
ns
tLZOE
OE LOW to Low Z
0
0
ns
tHZOE
OE HIGH to High Z[7, 8]
20
25
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z
[8]
5
5
ns
tHZCE
CE1 HIGH to High Z, CE2 LOW to High Z
[7, 8]
20
25
ns
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
0
0
ns
tPD
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
55
70
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
50
ns
tSD
Data Set-Up to Write End
45
55
ns
Shaded areas contain advance information
Notes:
5.
Tested initially and after any design or process changes that may affect these parameters.
6.
Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100pF load capacitance.
7.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
62128-3
62128-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
≤ 5ns
≤ 5 ns
OUTPUT
R1 1800
R1 1800
R2
990
R2
990
639
Equivalent to:
THÉVENIN EQUIVALENT
1.77V


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