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UT62256CSC-35L Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers |
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1 / 12 page UTRON UT62256C Rev. 1.0 32K X 8 BIT LOW POWER CMOS SRAM ____________________________________________________________________________________________ UTRON TECHNOLOGY INC. P80027 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 FEATURES Access time : 35/70ns (max.) Low power consumption: Operating : 40/30 mA (typical.) Standby : 3mA (typical) normal 2uA (typical) L-version 1uA (typical) LL-version Single 5V power supply All inputs and outputs are TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP 28-pin 8mmx13.4mm STSOP FUNCTIONAL BLOCK DIAGRAM COLUMNI/O COLUMNDECODER ROW DECODER I/O CONTROL LOGIC CONTROL A4 I/O1 VSS VCC WE OE CE I/O8 . . . ... . . . A3 A14 A13 A12 A7 A6 A5 A8 A9 A2 A1 A0 A10 ... ... MEMORYARRAY 512ROWS×512COLUMNS A11 PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A14 Address Inputs I/O1 - I/O8 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input VCC Power Supply VSS Ground GENERAL DESCRIPTION The UT62256C is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT62256C is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application. The UT62256C operates from a single 5V power supply and all inputs and outputs are fully TTL compatible PIN CONFIGURATION A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 Vcc A8 A9 A11 A10 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 Vss PDIP/SOP 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 CE WE OE A13 A14 I/O4 A11 A9 A8 A13 I/O3 A10 A14 A12 A7 A6 A5 Vcc I/O8 I/O7 I/O6 I/O5 Vss I/O2 I/O1 A0 A1 A2 A4 A3 UT62256C STSOP 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 WE OE CE |
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