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XR32430/XR32431

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Rev 1A

Figure 7: Charge Pump - Phase 1

Phase 2

V- transfer — Phase two of the clock connects the negative

terminal of C2 to the VSS storage capacitor and the posi-

tive terminal of C2 to GND. This transfers a negative gener-

ated voltage to C3. This generated voltage is regulated to a

minimum voltage of -5.5V. Simultaneous with the transfer of

the voltage to C3, the positive side of capacitor C1 is

GND.

Figure 8: Charge Pump - Phase 2

Phase 3

V+ charge storage — The third phase of the clock is identi-

cal to the first phase — the charge transferred in C1 pro-

Figure 9: Charge Pump - Phase 3

Phase 4

V+ transfer — The fourth phase of the clock connects the

negative terminal of C2 to GND, and transfers this positive

generated voltage across C2 to C4, the V+ storage capaci-

tor. This voltage is regulated to +5.5V. At this voltage, the

internal oscillator is disabled. Simultaneous with the trans-

fer of the voltage to C4, the positive side of capacitor C1 is

GND, allowing the charge pump cycle to begin again. The

charge pump cycle will continue as long as the operational

conditions for the internal oscillator are present.

Figure 10: Charge Pump - Phase 4

in a no–load condition V+ and V– will be symmetrical. Older

charge pump approaches that generate V– from V+ will

show a decrease in the magnitude of V– compared to V+

due to the inherent inefficiencies in the design. The clock

rate for the charge pump typically operates at greater than

250kHz. The external capacitors can be as low as 0.1μF

with a 16V breakdown voltage rating.

The Exar-patented charge pumps are designed to operate

reliably with a range of low cost capacitors. Either polarized

or non polarized capacitors may be used. If polarized

capacitors are used they should be oriented as shown in

the Typical Applications Circuit. The V+ capacitor may be

connected to either ground or Vcc (polarity reversed.)

C1

C2

C4

C3

C1

C2

C4

C3

-5.5V

C1

C2

C4

C3

C1

C2

C4

C3

+5.5V