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LM5175QPWPTQ1 Datasheet(PDF) 3 Page - Texas Instruments |
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LM5175QPWPTQ1 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 37 page VIN EN/UVLO SLOPE SS COMP FB AGND RT/SYNC ISNS(+) ISNS(±) VOSNS DITH MODE VISNS 2 1 7 8 9 11 10 6 14 13 12 5 4 3 28 27 26 25 24 23 22 21 20 19 18 16 15 17 SW1 HDRV1 BOOT1 LDRV1 BIAS VCC PGND LDRV2 BOOT2 HDRV2 SW2 CS CSG PGOOD LM5175-Q1 HTSSOP-28 3 LM5175-Q1 www.ti.com SNVSAD9 – APRIL 2016 Product Folder Links: LM5175-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 6 Pin Configuration and Functions HTSSOP-28 PWP Package Top View Pin Functions PIN DESCRIPTION NO. NAME 1 EN/UVLO Enable pin. For EN/UVLO < 0.4 V, the LM5175-Q1 is in a low current shutdown mode. For 0.7 V < EN/UVLO < 1.23 V, the controller operates in standby mode in which the VCC regulator is enabled but the PWM controller is not switching. For EN/UVLO > 1.23 V, the PWM function is enabled, provided VCC exceeds the VCC UV threshold. 2 VIN The input supply pin to the IC. Connect VIN to a supply voltage between 3.5 V and 42 V. 3 VISNS VIN sense input. Connect to the input capacitor. 4 MODE Mode = GND, DCM, Hiccup Disabled (Set RMODE resistor to GND = 0 Ω) Mode = 1.00 V, DCM, Hiccup Enabled (Set RMODE resistor to GND = 49.9 k Ω) Mode = 1.85 V, CCM, Hiccup Enabled (Set RMODE resistor to GND = 93.1 k Ω) Mode = VCC, CCM, Hiccup Disabled (Set RMODE resistor to VCC = 0 Ω) 5 DITH A capacitor connected between the DITH pin and AGND is charged and discharged with a 10 uA current source. As the voltage on the DITH pin ramps up and down the oscillator frequency is modulated between –5% and +5% of the nominal frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync mode, the DITH pin voltage is ignored. 6 RT/SYNC Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock. 7 SLOPE A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable current mode operation in both buck and boost mode. 8 SS Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time. 9 COMP Output of the error amplifier. An external RC network connected between COMP and AGND compensates the regulator feedback loop. 10 AGND Analog ground of the IC. 11 FB Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter to the FB pin. |
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