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SP693ACN Datasheet(PDF) 8 Page - Exar Corporation |
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SP693ACN Datasheet(HTML) 8 Page - Exar Corporation |
8 / 24 page Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 8 Pin 1 — V BATT — Battery-Backup Input. Con- nect to the external battery supply or super- charging capacitor and charging circuit. If a backup battery is not provided, connect this pin to ground. Pin 2 —V OUT — Output Supply Voltage. VOUT connects to V CC when VCC is greater than V BATT and VCC is above the reset threshold. When V CC falls below V BATT and V CC is below the reset threshold, V OUT connects to V BATT. Connect a 0.1µF capacitor from VOUT to GND. Pin 3 — V CC — +5V Input Supply Voltage. Pin 4 — GND — Ground reference for all signals. Pin 5 — BATT ON — Battery On Output. Goes high when V OUT switches to VBATT. Goes low when V OUT switches to VCC. Connect the base of a PNP through a current-limiting resistor to BATT ON for V OUT current requirements greater than 250mA. Pin 6 — LOWLINE — Low Line Output. This output pin goes LOW when V CC falls below the reset threshold voltage. This output pin returns to its HIGH output as soon as V CC rises above the reset threshold voltage. PINOUT Pin 7 — OSC IN — External Oscillator Input. When OSC SEL is unconnected or driven HIGH, a 10 µA pull-up connects from V OUT to this input pin, the internal oscillator sets the reset and watchdog timeout periods, and this input pin selects between fast and slow watchdog timeout periods. When OSC SEL is driven LOW, the reset and watchdog timeout periods may be set either by a capacitor from this input pin to ground or by an external clock at this pin (refer to Figure 21). Pin 8 — OSC SEL — Oscillator Select. When OSC SEL is unconnected or driven HIGH, the internal oscillator sets the reset delay and watchdog timeout period. When OSC SEL is driven LOW, the external oscillator input pin, OSC IN, is enabled (refer to Table 1). This input pin has a 10 µA internal pull-up. Pin 9 — PFI — Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or V OUT when not used. Pin 10 — PFO — Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. Pin 11 — WDI — Watchdog Input. This is a three-level input pin. If WDI remains either HIGH or LOW for longer than the watchdog timeout period, WDO goes LOW and RESET is asserted for the reset timeout period. WDO remains LOW until the next transition at this input pin. Leaving this input pin unconnected disables the watchdog function. This input pin connects to an internal voltage divider between V OUT and ground, which sets it to mid-supply when left unconnected. VBATT VOUT Vcc GND BATT ON PFO PFI OSCIN RESET WDO CEIN CEOUT WDI LOWLINE 16 DIP/SO TOP VIEW 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Corporation RESET OSCSEL PIN ASSIGNMENTS |
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