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IDTCSP2510CPG Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDTCSP2510CPG Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 9 page 1 0ºC TO 85ºC TEMPERATURE RANGE IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER OCTOBER 2000 1999 Integrated Device Technology, Inc. DSC-5180/2 c IDTCSP2510C 0ºººººC TO 85ºººººC TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER DESCRIPTION: The CSP2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. ItisspecificallydesignedforusewithsynchronousDRAMs.TheCSP2510C operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control Ginput.WhentheGinputishigh,theoutputsswitchinphaseandfrequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CSP2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground. The CSP2510C is specified for operation from 0°C to +85°C. This device is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details. 21 Y9 PLL 3 5 8 9 4 Y0 Y1 Y2 Y3 Y4 15 17 20 16 Y5 Y6 Y7 Y8 24 13 23 AV DD FB IN CLK G 11 12 FBOUT FUNCTIONAL BLOCK DIAGRAM The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network required for PLL loop stability • Operates at 3.3V VDD • tpd Phase Error at 133MHz: < ±150ps • Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz • Spread Spectrum Compatible • Operating frequency 25MHz to 140MHz • Available in 24-Pin TSSOP package APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations |
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