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PCM1741 Datasheet(PDF) 10 Page - Texas Instruments |
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PCM1741 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 24 page PCM1741 10 SBAS175 FIGURE 5. Control Data Word Format for MDI. FIGURE 6. Register Write Operation. SERIAL CONTROL INTERFACE The serial control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial control interface is utilized to program the on-chip mode registers. The control interface includes MD (pin 13), MC (pin 14), and ML (pin 15). MD is the serial data input, used to program the mode registers, MC is the serial bit clock, used to shift data into the control port, and ML is the control port latch clock. REGISTER WRITE OPERATION All write operations for the serial control port use 16-bit data words. Figure 5 shows the control data word format. The most significant bit must be a “0”. There are seven bits, labeled IDX[6:0], that set the register index (or address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 6 shows the functional timing diagram for writing the serial control port. ML is held at a logic “1 ” state until a register needs to be written. To start the register write cycle, ML is set to logic “0”. Sixteen clocks are then provided on MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has completed, ML is set to logic “1” to latch the data into the indexed mode control register. CONTROL INTERFACE TIMING REQUIREMENTS See Figure 7 for a detailed timing diagram of the serial control interface. These timing parameters are critical for proper control port operation. FIGURE 4. Audio Interface Timing. SYMBOL PARAMETER MIN MAX UNITS tBCY BCK Pulse Cycle Time 32, 48, or 64fS(1) tBCH BCK High Level Time 35 ns tBCL BCK Low Level Time 35 ns tBL BCK Rising Edge to LRCK Edge 10 ns tLB LRCK Falling Edge to BCK Rising Edge 10 ns tDS DATA Set Up Time 10 ns tDH DATA Hold Time 10 ns NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.) LRCK BCK DATA 50% of V DD 50% of V DD 50% of V DD t BCH t BCL t LB t BL t DS t DH t BCY IDX5 IDX6 0 IDX4 IDX2 IDX3 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 MSB Register Index (or Address) Register Data LSB 0 D7 D6D5 D4 D3D2 0 IDX6 D1 D0 X XX IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ML MC MD |
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