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PCA9545ARGYR Datasheet(PDF) 6 Page - Texas Instruments |
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PCA9545ARGYR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 37 page PCA9545A SCPS147D – OCTOBER 2005 – REVISED JUNE 2014 www.ti.com 7.5 I 2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) STANDARD MODE FAST MODE I2C BUS I2C BUS UNIT MIN MAX MIN MAX fscl I2C clock frequency 0 100 0 400 kHz tsch I2C clock high time 4 0.6 μs tscl I2C clock low time 4.7 1.3 μs tsp I2C spike time 50 50 ns tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0(1) 0(1) μs ticr I2C input rise time 1000 20 + 0.1Cb (2) 300 ns ticf I2C input fall time 300 20 + 0.1Cb (2) 300 ns tocf I2C output fall time 10-pF to 400-pF bus 300 20 + 0.1Cb (2) 300 ns tbuf I2C bus free time between stop and start 4.7 1.3 μs tsts I2C start or repeated start condition setup 4.7 0.6 μs tsth I2C start or repeated start condition hold 4 0.6 μs tsps I2C stop condition setup 4 0.6 μs SCL low to SDA output low tvdL(Data) Valid-data time (high to low)(3) 1 1 μs valid SCL low to SDA output high tvdH(Data) Valid-data time (low to high)(3) 0.6 0.6 μs valid ACK signal from SCL low tvd(ack) Valid-data time of ACK condition 1 1 μs to SDA output low Cb I2C bus capacitive load 400 400 pF (1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. (2) Cb = total bus capacitance of one bus line in pF (3) Data taken using a 1-k Ω pull-up resistor and 50-pF load (see Figure 1) 6 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: PCA9545A |
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