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PC16550D

SNLS378C – JUNE 1995 – REVISED MAY 2015

PC16550D Universal Asynchronous Receiver/Transmitter With FIFOs

1 Features

3 Description

The PC16550D device is an improved version of the

1

•

Capable of Running All Existing 16450 Software.

original

16450

Universal

Asynchronous

•

Pin for Pin Compatible With the Existing 16450

Receiver/Transmitter (UART). Functionally identical to

Except for CSOUT (24) and NC (29). The Former

the 16450 on powerup (CHARACTER mode: can also

CSOUT and NC Pins Are TXRDY and RXRDY,

be reset to 16450 Mode under software control) the

Respectively.

PC16550D can be put into an alternate mode (FIFO

mode) to relieve the CPU of excessive software

•

After Reset, All Registers Are Identical to the

overhead.

16450 Register Set.

•

In this mode internal FIFOs are activated allowing 16

bytes (plus 3 bits of error data per byte in the RCVR

Each Buffered With 16 Byte FIFO’s to Reduce the

FIFO) to be stored in both receive and transmit

Number of Interrupts Presented to the CPU.

modes. All the logic is on chip to minimize system

•

Adds or Deletes Standard Asynchronous

overhead and maximize system efficiency. Two pin

Communication Bits (Start, Stop, and Parity) to or

functions have been changed to allow signalling of

From the Serial Data.

DMA transfers.

•

Holding and Shift Registers in the 16450 Mode

The UART performs serial-to-parallel conversion on

Eliminate the Need for Precise Synchronization

data characters received from a peripheral device or

Between the CPU and Serial Data.

a MODEM, and parallel-to-serial conversion on data

•

Independently Controlled Transmit, Receive, Line

characters received from the CPU. The CPU can

Status, and Data Set Interrupts.

read the complete status of the UART at any time

during the functional operation. Status information

•

Programmable Baud Generator Divides Any Input

reported includes the type and condition of the

transfer operations being performed by the UART, as

Clock.

well as any error conditions (parity, overrun, framing,

•

Independent Receiver Clock Input.

or break interrupt).

•

MODEM Control Functions (CTS, RTS, DSR,

Device Information(1)

DTR, RI, and DCD).

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

Fully Programmable Serial-Interface

PLCC (44)

17.53 mm x 17.53 mm

Characteristics

PC16550D

PDIP (40)

52.58 mm x 13.97 mm

–

5-, 6-, 7-, or 8-Bit Characters

(1) For all available packages, see the orderable addendum at

–

Even, Odd, or No-Parity Bit Generation and

the end of the datasheet.

Detection

–

1-, 1 1/2-, or 2-Stop Bit Generation

Basic Configuration

–

Baud Generation (DC to 1.5 M Baud).

•

False Start Bit Detection.

•

Complete Status Reporting Capabilities.

•

TRI-STATE TTL Drive for the Data and Control

Buses.

•

Line Break Generation and Detection.

•

Internal Diagnostic Capabilities

–

Loopback Controls for Communications Link

Fault Isolation

–

Break, Parity, Overrun, Framing Error

Simulation.

•

Full Prioritized Interrupt System Controls.

2 Applications

Modems or Generic UART Communication

(1)

This part is patented

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.