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SN74AHC1G32DCKRE4 Datasheet(PDF) 10 Page - Texas Instruments

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Part # SN74AHC1G32DCKRE4
Description  SN74AHC1G32 Single 2-Input Positive-OR Gate
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74AHC1G32DCKRE4 Datasheet(HTML) 10 Page - Texas Instruments

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Vcc
Unused Input
Input
Output
Input
Unused Input
Output
SN74AHC1G32
SCLS317O – MARCH 1996 – REVISED JULY 2014
www.ti.com
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1
μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1
μf and a
1
μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Figure 6. Layout Diagram
10
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Copyright © 1996–2014, Texas Instruments Incorporated
Product Folder Links: SN74AHC1G32


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