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DP8570A Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP8570A Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 26 page  General Description (Continued) The DP8570A’s interrupt structure provides four basic types of interrupts Periodic AlarmCompare Timer and Power Fail Interrupt mask and status registers enable the masking and easy determination of each interrupt One dedicated general purpose interrupt output is provided A second interrupt output is available on the Multiple Func- tion Output (MFO) pin Each of these may be selected to generate an interrupt from any source Additionally the MFO pin may be programmed to be either as oscillator out- put or Timer 0’s output Pin Description CS RD WR (Inputs) These pins interface to mP control lines The CS pin is an active low enable for the read and write operations Read and Write pins are also active low and enable reading or writing to the TCP All three pins are disabled when power failure is detected However if a read or write is in progress at this time it will be allowed to com- plete its cycle A0 – A4 (Inputs) These 5 pins are for register selection They individually control which location is to be accessed These inputs are disabled when power failure is detected OSC IN (Input) OSC OUT (Output) These two pins are used to connect the crystal to the internal parallel resonant oscillator The oscillator is always running when power is applied to VBB and VCC and the correct crystal select bits in the Real Time Mode Register have been set MFO (Output) The multi-function output can be used as a second interrupt output for interrupting the mP This pin can also provide an output for the oscillator or the internal Timer 0 The MFO output can be programmed active high or low open drain or push-pull If in battery backed mode and a pull-up resistor is attached it should be connected to a volt- age no greater than VBB This pin is configured open drain during battery operation (VBB l VCC) INTR (Output) The interrupt output is used to interrupt the processor when a timing event or power fail has occurred and the respective interrupt has been enabled The INTR output can be programmed active high or low push-pull or open drain If in battery backed mode and a pull-up resistor is attached it should be connected to a voltage no greater than VBB This pin is configured open drain during battery operation (VBB l VCC) The output is a DC voltage level To clear the INTR writea1tothe appropriate bit(s) in the Main Status Register D0 – D7 (InputOutput) These 8 bidirectional pins connect to the host mP’s data bus and are used to read from and write to the TCP When the PFAIL pin goes low and a write is not in progress these pins are at TRI-STATE PFAIL (Input) In battery backed mode this pin can have a digital signal applied to it via some external power detection logic When PFAIL e logic 0 the TCP goes into a lockout mode in a minimum of 30 ms or a maximum of 63 ms unless lockout delay is programmed In the single power supply mode this pin is not useable as an input and should be tied to VCC Refer to section on Power Fail Functional Descrip- tion VBB (Battery Power Pin) This pin is connected to a back- up power supply This power supply is switched to the inter- nal circuitry when the VCC becomes lower than VBB Utiliz- ing this pin eliminates the need for external logic to switch in and out the back-up power supply If this feature is not to be used then this pin must be tied to ground the TCP pro- grammed for single power supply only and power applied to the VCC pin TCK G1 G0 (Inputs) T1 (Output) TCK is the clock input to both timers when they have an external clock selected In modes 0 1 and 2 G0 and G1 are active low enable inputs for timers 0 and 1 respectively In mode 3 G0 and G1 are positive edge triggers to the timers T1 is dedicated to the timer 1 output The T1 output can be programmed active high or low push-pull or open drain Timer 0 output is avail- able through MFO pin if desired If in battery backed mode and a pull-up resistor is attached to T1 it should be con- nected to a voltage no greater than VBB The T1 pin is con- figured open drain during battery operation (VBB l VCC) VCC This is the main system power pin GND This is the common ground power pin for both VBB and VCC Connection Diagrams Dual-In-Line TLF8638 – 5 Top View Order Number DP8570AN See NS Package Number N28B Plastic Chip Carrier TLF8638 – 6 Top View Order Number DP8570AV See NS Package Number V28A 5 |
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Similar Description - DP8570A |
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