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DP8464BV-3 Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP8464BV-3
Description  Disk Pulse Detector
Download  26 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP8464BV-3 Datasheet(HTML) 11 Page - National Semiconductor (TI)

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Application Information (Continued)
AUTOMATIC GAIN CONTROL (AGC)
The Automatic Gain Control holds the signal level at the
Gate Channel Input at a constant level by controlling the
gain of the Gain Controlled Amplifier This is necessary be-
cause the amplitude of the input signal will vary with track
location variations in the magnetic film and differences in
the actual recording amplitude The Gain Controlled Amplifi-
er is designed for a maximum 4 Vpp differential output To
prevent the Gain Controlled Amplifier from saturating the
VREF level must be set so the maximum amplifier output
voltage is 4 Vpp The AGC will force the differential peak-to-
peak signal on the Gate Channel Input to be four times the
voltage applied to the VREF pin Normally some kind of filter
is connected between the Gain Controlled Amplifier’s output
and the Gate Channel Input Typically this filter hasa6dB
insertion loss in its pass band Since the AGC holds the
amplitude at the Gate Channel Input constant this 6 dB loss
through the Gate Channel filter will cause the Gain Con-
trolled Amplifier’s output to be 6 dB larger than the Gate
Channel Input
The AGC loop starts out in the high gain mode When the
input signal is larger than expected the AGC loop will quick-
ly reduce the amplifier gain so the peak-to-peak differential
voltage on the Gate Channel Input remains four times the
voltage on VREF If the input amplitude suddenly drops the
AGC loop will slowly increase the amplifier gain until the
differential peak-to-peak Gate Channel Input voltage again
reaches four times VREF The AGC loop requires several
peaks to react to an increased input signal In order to re-
cover the exact peak timing during this transition the VOUT
level must be set somewhat lower than the maximum of
4 Vpp For instance if the VREF is 05V and if the loss in the
gate channel filter is 6 dB then the Amp Output is 4 Vpp If
the Amp Input suddenly increases 30% the amplifier may
saturate and the timing for a few peaks may be disturbed
until the AGC reduces the amplifier gain If the peak detec-
tion is critical during this time the system may fail The prop-
er operation for this example is to set the VREF at 035V so
the amplifier will not saturate if the input suddenly increases
30%
A simplified circuit of the AGC block is shown in
Figure 6
When the full wave rectified signal from the Gate Channel
Input is greater than VREF the voltage on the collector of
transistor T1 will increase and charge up the external ca-
pacitor CAGC through T2 The typical available charging cur-
rent is 25 mA Conversely if this input is less than VREF
transistor T2 will be off so the capacitor CAGC will be dis-
charged by the base current going into the Darlington T3
and T4 This discharge current is approximately 1 mA The
voltage across CAGC controls the gain of the Gain Con-
trolled Amplifier This voltage will vary from typically 34V at
the highest gain to 45V at the lowest gain
When the AGC circuit has not received an input signal for a
long time the base current of the Darlington will discharge
the external CAGC to 34V The amplifier will now be at its
highest gain When a large signal comes in the external
CAGC will be charged up with the 24 mA from T2 thereby
reducing the gain of the amplifier The formula I e C c
(dVdt) can be used to calculate the time required for the
amplifier to go from a gain of 200 to a gain of 6 For in-
stance if CAGC e 001 mf the charging current I is 24 mA
and the dV required for the amplifier to go through its gain
range is 11V then
dt e (001 mF c 11V)(24 mA) or 46 ms
In reality the gain does not change this quickly since the
CAGC would only be charging during a portion of the input
waveform
By using the same argument the time required to increase
the amplifier gain after the input has been suddenly reduced
can be calculated This time the discharging current is only
1 maso
dt e (001 mF c 11V)1 mA) or 11 ms
TLF5283 – 11
FIGURE 6 Simplified AGC Circuit
11


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