K6X4008T1F Family

CMOS SRAM

Revision 1.0

September 2003

2

512K

×8 bit Low Power and Low Voltage CMOS Static RAM

GENERAL DESCRIPTION

The K6X4008T1F families are fabricated by SAMSUNG

′s

advanced full CMOS process technology. The families support

various operating temperature range and have various pack-

age types for user flexibility of system design. The families also

support low data retention voltage for battery back-up operation

with low data retention current.

FEATURES

• Process Technology: Full CMOS

• Organization: 512K×8

• Power Supply Voltage: 2.7~3.6V

• Low Data Retention Voltage: 2V(Min)

• Three State Outputs

• Package Type: 32-SOP-525, 32-TSOP2-400F/R

32-TSOP1-0813.4F

PIN DESCRIPTION

Name

Function

Name

Function

Vcc

Power

WE

Write Enable Input

Vss

Ground

CS

Chip Select Input

OE

Output Enable Input

PRODUCT FAMILY

1. This parameter is measured in the voltage range of 3.0V~3.6V with 30pF test load.

2. This parameter is measured with 30pF test load.

Product Family Operating Temperature

Vcc

Range

Speed

Power Dissipation

PKG Type

Standby

Operating

K6X4008T1F-B

Commercial(0~70

°C)

2.7~3.6V

10

µA

25mA

32-SOP-525, 32-TSOP1-0813.4F

32-TSOP2-400F/R

K6X4008T1F-F

Industrial(-40~85

°C)

10

µA

K6X4008T1F-Q

Automotive(-40~125

°C)

20

µA

32-SOP-525, 32-TSOP1-0813.4F

32-TSOP2-400F

FUNCTIONAL BLOCK DIAGRAM

32-SOP

(Forward)

32-TSOP2

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

VSS

VCC

A15

WE

A13

A8

A9

A11

OE

A10

CS

I/O8

I/O7

I/O6

I/O5

I/O4

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32-TSOP2

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

VSS

VCC

A15

WE

A13

A8

A9

A11

OE

A10

CS

I/O8

I/O7

I/O6

I/O5

I/O4

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

(Reverse)

A18

A17

A17

A18

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array

I/O Circuit

Column select

Clk gen.

Row

select

CS

WE

Data

cont

Data

cont

OE

A11

A9

A8

A13

WE

A17

A15

VCC

A18

A16

A14

A12

A7

A6

A5

A4

OE

A10

CS

I/O8

I/O7

I/O6

I/O5

I/O4

VSS

I/O3

I/O2

I/O1

A0

A1

A2

A3

(Forward)

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Control

logic

Row

Addresses

Column Addresses