LM27966

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SNVS448B – JULY 2006 – REVISED MAY 2013

CIRCUIT DESCRIPTION

OVERVIEW

The LM27966 is a white LED driver system based upon an adaptive 1.5×/1× CMOS charge pump capable of

supplying up to 180mA of total output current. With two controlled banks of constant current sinks (Main and

AUX), the LM27966 is an ideal solution for platforms requiring a single white LED driver for main display and

indicator lighting. The tightly matched current sinks ensure uniform brightness from the LEDs across the entire

small-format display.

Each LED is configured in a common anode configuration, with the peak drive current being programmed

the brightness within the individual current sink banks. For Main Display LEDs, 32 levels of brightness control are

available. The brightness control is achieved through a mix of analog and pulse width modulated (PWM)

CIRCUIT COMPONENTS

Charge Pump

regulated charge pump has both open loop and closed loop modes of operation. When the device is in open

regulation based on LED forward voltage and load requirements. This allows the charge pump to stay in the

most efficient gain (1x) over as much of the input voltage range as possible, reducing the power consumed from

the battery.

LED Forward Voltage Monitoring

The LM27966 has the ability to switch converter gains (1x or 1.5x) based on the forward voltage of the LED load.

This ability to switch gains maximizes efficiency for a given load. Forward voltage monitoring occurs on all diode

pump will then switch to the gain of 1.5x. This switchover ensures that the current through the LEDs never

becomes pinched off due to a lack of headroom on the current sources.

Diode pin D5 can have the diode sensing circuity disabled through the general purpose register if D5 is not going

to be used.

RESET Pin

The LM27965 has a hardware reset pin (RESET) that allows the device to be disabled by an external controller

to prevent an unwanted reset. When the RESET is driven low (logic ’0’), all internal control registers reset to the

default states and the part becomes disabled. Please see the Electrical Characteristics section of the datasheet

for required voltage thresholds.

DATA VALIDITY

The data on SDIO line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

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