SDIO

SCL

S

P

P

STO

condition

SCL

SDIO

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LM27965

SNVS380B – MAY 2006 – REVISED FEBRUARY 2013

www.ti.com

Figure 10. Data Validity Diagram

on SDIO. Using a larger pull-up resistor results in lower switching current with slower edges, while using a

smaller pull-up results in higher switching currents with faster edges.

START AND STOP CONDITIONS

defined as SDIO signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as

START conditions are equivalent, function-wise.

Figure 11. Start and Stop Conditions

TRANSFERING DATA

Every byte put on the SDIO line must be eight bits long, with the most significant bit (MSB) transferred first. Each

byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the

master. The master releases the SDIO line (HIGH) during the acknowledge clock pulse. The LM27965 pulls

down the SDIO line during the 9th clock pulse, signifying an acknowledge. The LM27965 generates an

acknowledge after each byte is received.

eighth bit which is a data direction bit (R/W). The LM27965 address is 36h (38h for -M version). For the eighth

bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data

will be written. The third byte contains data to write to the selected register.

10

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