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LM3S102 Datasheet(PDF) 9 Page - Texas Instruments |
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LM3S102 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 487 page  List of Figures Figure 1-1. Stellaris LM3S102 Microcontroller High-Level Block Diagram ................................. 33 Figure 1-2. LM3S102 Controller System-Level Block Diagram ................................................. 39 Figure 2-1. CPU Block Diagram ............................................................................................. 42 Figure 2-2. TPIU Block Diagram ............................................................................................ 43 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 45 Figure 2-4. Bit-Band Mapping ................................................................................................ 64 Figure 2-5. Data Storage ....................................................................................................... 65 Figure 2-6. Vector Table ........................................................................................................ 71 Figure 2-7. Exception Stack Frame ........................................................................................ 73 Figure 4-1. JTAG Module Block Diagram .............................................................................. 125 Figure 4-2. Test Access Port State Machine ......................................................................... 129 Figure 4-3. IDCODE Register Format ................................................................................... 133 Figure 4-4. BYPASS Register Format ................................................................................... 134 Figure 4-5. Boundary Scan Register Format ......................................................................... 134 Figure 5-1. Basic RST Configuration .................................................................................... 137 Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 138 Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 138 Figure 5-4. Main Clock Tree ................................................................................................ 141 Figure 6-1. Flash Block Diagram .......................................................................................... 185 Figure 7-1. GPIO Module Block Diagram .............................................................................. 204 Figure 7-2. GPIO Port Block Diagram ................................................................................... 208 Figure 7-3. GPIODATA Write Example ................................................................................. 209 Figure 7-4. GPIODATA Read Example ................................................................................. 209 Figure 8-1. GPTM Module Block Diagram ............................................................................ 246 Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 250 Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 251 Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 252 Figure 9-1. WDT Module Block Diagram .............................................................................. 282 Figure 10-1. UART Module Block Diagram ............................................................................. 306 Figure 10-2. UART Character Frame ..................................................................................... 307 Figure 11-1. SSI Module Block Diagram ................................................................................. 345 Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 348 Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 349 Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 349 Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 350 Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 351 Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 351 Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 352 Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 353 Figure 11-10. MICROWIRE Frame Format (Single Frame) ........................................................ 353 Figure 11-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 354 Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 355 Figure 12-1. I2C Block Diagram ............................................................................................. 384 Figure 12-2. I2C Bus Configuration ........................................................................................ 385 Figure 12-3. START and STOP Conditions ............................................................................. 385 Figure 12-4. Complete Data Transfer with a 7-Bit Address ....................................................... 386 9 July 14, 2014 Texas Instruments-Production Data Stellaris ® LM3S102 Microcontroller |
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