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SN65LVDS150PWR Datasheet(PDF) 5 Page - Texas Instruments

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Part # SN65LVDS150PWR
Description  MuxIt PLL FREQUENCY MULTIPLIER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65LVDS150PWR Datasheet(HTML) 5 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
SN65LVDS150
SLLS443 – DECEMBER 2000
Terminal Functions
TERMINAL
I/O
TYPE
DESCRIPTION
NAME
NO.
BSEL
11
I
LVTTL
Band select. Used to optimize VCO performance for minimum M-clock jitter: See
recommended fmax in the frequency multiplier value table.
CRI+, CRI–
2, 3
I
LVDS
Clock reference input. This is the reference clock signal for the PLL frequency multiplier.
EN
17
I
LVTTL
Enable input. Used to disable the device to a low power state. A high level input enables the
device, a low level input disables the device.
GND
5, 12, 18,
I
NA
Circuit ground
22, 24
LCRO–,
13, 14
O
LVDS
Link clock reference output. This is the data block synchronization clock signal from the PLL
LCRO+
frequency multiplier.
LCRO_EN
16
I
LVTTL
LCRO enable. Used to turn off the LCRO outputs when they are not used. A high level input
enables the LCRO output; a low level input disables the LCRO output.
LVO
15
O
LVTTL
Lock/valid output. This is signal required for proper Muxlt system operation. It is to be directly
connected to the LVI inputs of SN65LVDS151 or SN65LVDS152 devices. It is used to inhibit
the operation of those devices until after the PLL has stabilized. It remains at a low level
following a reset until the PLL has become phase locked. A low to high-level transition
indicates phase lock has occurred.
M1–M5
6–10
I
LVTTL
Multiplier value selection inputs. These inputs determine the frequency multiplication ratio M.
MCO–, MCO+
19, 20
O
LVDS
M-clock output. This is the high frequency multiplied clock output from the PLL frequency
multiplier. It is used by the companion serializer or deserializer devices to synchronizes the
transmission or reception of data
NC
21, 23,
NA
These pins are not connected and may be left open.
26–28
VCC
1, 25
NA
Supply voltage
VT
4
NA
Voltage reference. A VCC/2 reference supplied for the unused CRI input when operated in a
single-ended mode.
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
Supply voltage range(2)
–0.5 V to 4 V
EN, BSEL, LCRO_EN, or M1-M5 inputs
–0.5 V to 6 V
Voltage range
CRI input
–0.5 V to 4 V
LCRO±, MCO± outputs
–0.5 V to 4 V
Human body model (CRI±, LCRO±, MCO±,and GND(3)
±12 kV
Electrostatic discharge
All pins
±2 kV
Charged-device model (all pins)(4)
±500 V
Continuous total power dissipation
See Dissipation Rating Table
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
(3)
Tested in accordance with JEDEC Standard 22, Test method A114-B.
(4)
Tested in accordance with JEDEC Standard 22, Test method C101.
5
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