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SN65LVDS93A Datasheet(PDF) 9 Page - Texas Instruments |
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SN65LVDS93A Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 35 page  CLKL Signal PRBS Data Signal t - Time - 1ns/div k f - Clock Frequency - MHz clk 50 10 30 50 70 90 110 130 20 30 70 40 90 60 80 V = 3.6V CC V = 3.3V CC V = 3V CC 100 300 0.01 0.10 10 f - Input Modular Frequency - MHz (mod) 0 100 500 200 600 400 800 700 1 Output Jitter Input Jitter SN65LVDS93A-Q1 www.ti.com SLLSEM1B – FEBRUARY 2015 – REVISED APRIL 2015 6.8 Typical Characteristics CLK Frequency During Test = 100 MHz Total Device Current (Using Grayscale pattern) Over Pixel Clock Frequency Figure 3. Average Grayscale ICC vs Clock Frequency Figure 4. Output Clock Jitter vs Input Clock Jitter Clock Signal = 135 MHz Figure 5. Typical PRBS Output Signal Over One Clock Period Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN65LVDS93A-Q1 |
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