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SN65LVDS93DGG Datasheet(PDF) 7 Page - Texas Instruments |
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SN65LVDS93DGG Datasheet(HTML) 7 Page - Texas Instruments |
7 / 19 page CL = 10 pF Max (2 Places) 49.9 Ω ± 1% (2 Places) VOC VOD YP YM VOD(H) VOC(SS) VOC(SS) VOD(L) 100% 80% 20% 0% 0 V VOC(PP) tr tf 0 V (a) SCHEMATIC (b) WAVEFORMS NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. tc NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with CLKSEL low shown. CLKIN Even Dn Odd Dn SN65LVDS93 www.ti.com ................................................................................................................................................................. SLLS302G – MAY 1998 – REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION (continued) Figure 3. Test Load and Voltage Definitions for LVDS Outputs Figure 4. Worst-Case Test Pattern (CLKSEL Low Shown) Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s) :SN65LVDS93 |
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