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SN65LV1023ADBG4 Datasheet(PDF) 9 Page - Texas Instruments |
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SN65LV1023ADBG4 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 29 page  www.ti.com SERIALIZER TIMING REQUIREMENTS FOR TCLK SERIALIZER SWITCHING CHARACTERISTICS DESERIALIZER TIMING REQUIREMENTS FOR REFCLK SN65LV1023A SN65LV1224A SLLS570D – JUNE 2003 – REVISED JANUARY 2005 over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tTCP Transmit clock period 15.15 T 100 ns tTCIH Transmit clock high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns tt(CLK) TCLK input transition time 3 6 ns tJIT TCLK input jitter See Figure 18 150 ps (RMS) Frequency Tolerance –100 100 ppm over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tTLH(L) LVDS low-to-high transition time 0.2 0.4 ns RL = 27 Ω, CL = 10 pF to GND, See Figure 5 tLTHL(L) LVDS high-to-low transition time 0.25 0.4 ns tsu(DI) DIN0-DIN9 setup to TCLK 0.5 ns RL = 27 Ω, CL = 10 pF to GND, See Figure 8 tsu(DI) DIN0-DIN9 hold from TCLK 4 ns td(HZ) DO± high-to-high-impedance-state delay 2.5 5 td(LZ) DO± low-to-high-impedance-state delay 2.5 5 RL = 27 Ω, CL = 10 pF to GND, See DO± high-to-high-impedance-state-to-high ns td(ZH) 5 10 Figure 9 delay DO± high-to-high-impedance-state-to-low td(ZL) 6.5 10 delay tw(SPW) SYNC pulse duration 6×tTCP ns RL = 27 Ω, See Figure 11 t(PLD) Serializer PLL lock time 1026×tTCP ns td(S) Serializer delay RL = 27 Ω, See Figure 12 tTCP+1 tTCP+2 tTCP+3 ns 10 MHz 230 tDJIT Deterministic jitter RL = 27 Ω, CL = 10 pF to GND ps 66 MHz 150 ps tRJIT Random jitter RL = 2.7 Ω, CL = 10 pF to GND 10 19 (RMS) over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRFCP REFCLK period 15.1 T 100 ns 5 tRFDC REFCLK duty cycle 30% 50% 70% tt(RF) REFCLK transition time 3 6 ns Frequency tolerance 100 +100 ppm 9 Submit Documentation Feedback |
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