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SN65LV1021DBG4 Datasheet(PDF) 5 Page - Texas Instruments |
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SN65LV1021DBG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 22 page www.ti.com POWER DOWN HIGH-IMPEDANCE MODE SN65LV1021 SN65LV1212 SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUTx data is valid when LOCK is low, otherwise ROUT0-ROUT9 is invalid. The ROUT0-ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input. The ROUT0-ROUT9, LOCK and RCLK outputs can drive a maximum of three CMOS input gates (15-pF load, total for all three) with a 40-MHz clock. When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the power-down mode, a low-power sleep mode, to reduce power consumption. The deserializer enters power down when you drive PWRDN and REN low. The serializer enters power down when the PWRDN is driven low. In power down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high. Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer initializes and drives LOCK high until lock to the LVDS clock occurs. The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins (DO+ and DO-) into a high-impedance state. When you drive DEN high, the serializer returns to its previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins (ROUT0-ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting the state of the PLL. Deserializer Truth Table INPUTS OUTPUTS PWRDN REN ROUT[0:9] LOCK(1), (2) RCLK(3) H H Z H Z H H Active L Active L X Z Z Z H L Z Active Z (1) LOCK output reflects the state of the deserializer with regard to the selected data stream. (2) ROUT and RCLK are 3-stated when LOCK is asserted high. (3) RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by RCLK_R/F. 5 |
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