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TAS5010 Datasheet(PDF) 9 Page - Texas Instruments |
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TAS5010 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 18 page TAS5010 SLAS328 – SEPTEMBER 2001 9 www.ti.com functional description (continued) de-emphasis selection De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 3 for de-emphasis selection description. Table 3. De-Emphasis Selection DEM_SEL DEM_EN DESCRIPTION 0 0 De-emphasis disabled 0 1 De-emphasis enabled for Fs = 44.1 kHz 1 1 De-emphasis enabled for Fs = 48 kHz 1 0 Forbidden modey. Do not use. error status reporting (VALID_L and VALID_R) The following is a list of the error conditions that will cause the VALID_L and VALID_R pins to be asserted low: D No clocks D Clock phase errors When either of the above conditions is met, the VALID_L and VALID_R goes low and the PWM outputs go to the hard mute state. If the error condition is removed, the TAS5010 is reinitialized and the VALID_L and VALID_R pins are asserted high. serial interface formats The TAS5010 is compatible with eight different serial interfaces. Available interface options are IIS, right justified, left justified, and DSP frame. Table 4 indicates how these options are selected using the MOD0, MOD1, and MOD2 pins. Table 4. Hardware Selection of Serial Audio Modes MODE MOD2 PIN MOD1 PIN MOD0 PIN SERIAL INTERFACE SDIN 0 0 0 0 16 bit, MSB first; right justified 1 0 0 1 20 bit, MSB first; right justified 2 0 1 0 24 bit, MSB first; right justified 3 0 1 1 16 bit IIS 4 1 0 0 20 bit IIS 5 1 0 1 24 bit IIS 6 1 1 0 16 bit MSB first, left justified 7 1 1 1 16 bit DSP frame The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0s. |
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