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PCA9545 Datasheet(PDF) 11 Page - NXP Semiconductors |
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PCA9545 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 14 page  Philips Semiconductors Product data PCA9545 4-channel I2C switch with interrupt logic and reset 2002 Mar 28 11 853-2302 27311 AC CHARACTERISTICS SYMBOL PARAMETER STANDARD-MODE I2C-BUS FAST-MODE I2C-BUS UNIT MIN MAX MIN MAX tpd Propagation delay from SDA to SDn or SCL to SCn — 0.31 — 0.31 ns fSCL SCL clock frequency 0 100 0 400 kHz tBUF Bus free time between a STOP and START condition 4.7 — 1.3 — µs tHD;STA Hold time (repeated) START condition After this period, the first clock pulse is generated 4.0 — 0.6 — µs tLOW LOW period of the SCL clock 4.7 — 1.3 — µs tHIGH HIGH period of the SCL clock 4.0 — 0.6 — µs tSU;STA Set-up time for a repeated START condition 4.7 — 0.6 — µs tSU;STO Set-up time for STOP condition 4.0 — 0.6 — µs tHD;DAT Data hold time 02 3.45 02 0.9 µs tSU;DAT Data set-up time 250 — 100 — ns tR Rise time of both SDA and SCL signals — 1000 20 + 0.1Cb3 300 ns tF Fall time of both SDA and SCL signals — 300 20 + 0.1Cb3 300 µs Cb Capacitive load for each bus line — 400 — 400 µs tSP Pulse width of spikes which must be suppressed by the input filter — 50 — 50 ns tVD:DATL Data valid (HL) — 1 — 1 µs tVD:DATH Data valid (LH) — 0.6 — 0.6 µs tVD:ACK Data valid Acknowledge — 1 — 1 µs INT tiv INTn to INT active valid time — 4 — 4 µs tir INTn to INT inactive delay time — 2 — 2 µs Lpwr LOW level pulse width rejection or INTn inputs 1 — 1 — µs Hpwr HIGH level pulse width rejection or INTn inputs 0.5 — 0.5 — µs RESET tWL(rst) Pulse width low reset 4 — 4 — ns trst Reset time (SDA clear) 500 — 500 — ns tREC:STA Recovery to Start 0 — 0 — ns NOTES: 1. Pass gate propagation delay is calculated from the 20 Ω typical RON and the 15 pF load capacitance. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3. Cb = total capacitance of one bus line in pF. tSP tBUF tHD;STA P P S tLOW tR tHD;DAT tF tHIGH tSU;DAT tSU;STA Sr tHD;STA tSU;STO SDA SCL SU00645 Figure 13. Definition of timing on the I2C-bus |
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