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MAX191AMRG Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX191AMRG Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 24 page Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down _______________________________________________________________________________________ 5 PARAMETER SCLK to SCLKOUT Delay CONDITIONS 160 UNITS ns CS to DOUT Three-State 100 ns SYMBOL CS or RD Setup Time CS or RD Hold Time ns 150 ns t20 t19 t17 t16 TIMING CHARACTERISTICS (Figures 6–10) (continued) (VDD =5V ±5%, VSS = 0V or -5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Note 14) 10 MAX191C/E MIN TYP MAX 180 110 10 150 MAX191M MIN TYP MAX 200 120 10 150 310 350 SCLK to SSTRB Delay 260 ns t23 260 280 SCLK to DOUT Delay 240 ns t22 130 SCLKOUT to DOUT Delay 100 ns t21 150 Note 1: Performance at power-supply tolerance limits guaranteed by power-supply rejection test. Note 2: VDD = 5V, VSS = 0V, FS = VREF. Note 3: FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB. Note 4: Gain-Error Tempco = ∆GE is the gain-error change from TA = +25°C to TMIN or TMAX. Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Note 6: Guaranteed by design, not production tested. Note 7: AIN+, AIN- must not exceed supplies for specified accuracy. Note 8: VREF TC = ∆T, where ∆VREF is reference-voltage change from TA = +25°C to TMIN or TMAX. Note 9: Output current should not change during conversion. This current is in addition to the current required by the internal DAC. Note 10: REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V. This will typically result in a 1.7 times larger change in the REF output (Figure 19a). Note 11: This current is included in the PD supply current specification. Note 12: Floating the PD pin guarantees external compensation mode. Note 13: VREF = 4.096V, external reference. Note 14: All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Note 15: t3 and t6 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. Note 16: t7 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. TA = +25°C MIN TYP MAX |
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