Low-Power, 12-Bit Sampling ADC

with Internal Reference and Power-Down

______________________________________________________________________________________

11

DATA

HOLD*

TRACK

NEW DATA

D11–D8

*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.

BUSY

RD

CS

HBEN

NEW DATA

D7–D0

OLD DATA

D7–D0

Figure 7. Slow-Memory Mode Timing

HBEN

CS

RD

BUSY

DATA

HOLD*

TRACK

OLD DATA

D7–D0

NEW DATA

D11–D8

NEW DATA

D7–D0

*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.

Figure 8. ROM Mode Timing