AT94K40AL-25BQI datasheet(5/192 Pages) ATMEL

Part #	AT94K40AL-25BQI

Description	5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE

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Manufacturer	ATMEL [ATMEL Corporation]

Direct Link	http://www.atmel.com

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AT94K Series FPSLIC

Rev. 1138F–FPSLI–06/02

FPGA Core

The AT40K core can be used for high-performance designs, by implementing a variety of com-

pute-intensive arithmetic functions. These include adaptive finite impulse response (FIR)

filters, fast Fourier transforms (FFT), convolvers, interpolators, and discrete-cosine transforms

(DCT) that are required for video compression and decompression, encryption, convolution

and other multimedia applications.

Fast, Flexible and

Efficient SRAM

The AT40K core offers a patented distributed 10 ns SRAM capability where the RAM can be

used without losing logic resources. Multiple independent, synchronous or asynchronous,

dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s

macro generator tool.

Fast, Efficient

Array and Vector

Multipliers

The AT40K cores patented 8-sided core cell with direct horizontal, vertical and diagonal cell-

to-cell connections implements ultra-fast array multipliers without using any busing resources.

The AT40K core’s Cache Logic capability enables a large number of design coefficients and

variables to be implemented in a very small amount of silicon, enabling vast improvement in

system speed.

Cache Logic

Design

The AT40K FPGA core is capable of implementing Cache Logic (dynamic full/partial logic

reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As

new logic functions are required, they can be loaded into the logic cache without losing the

data already there or disrupting the operation of the rest of the chip; replacing or complement-

ing the active logic. The AT40K FPGA core can act as a reconfigurable resource within the

FPSLIC environment.

Automatic

Component

Generators

The AT40K is capable of implementing user-defined, automatically generated, macros; speed

and functionality are unaffected by the macro orientation or density of the target device. This

enables the fastest, most predictable and efficient FPGA design approach and minimizes

design risk by reusing already proven functions. The Automatic Component Generators work

seamlessly with industry-standard schematic and synthesis tools to create fast, efficient

designs.

The patented AT40K architecture employs a symmetrical grid of small yet powerful cells con-

nected to a flexible busing network. Independently controlled clocks and resets govern every

column of four cells. The FPSLIC device is surrounded on three sides by programmable I/Os.

Core usable gate counts range from 5,000 to 40,000 gates and 436 to 2,864 registers. Pin

locations are consistent throughout the FPSLIC family for easy design migration in the same

package footprint.

The Atmel AT40K FPGA core architecture was developed to provide the highest levels of per-

formance, functional density and design flexibility. The cells in the FPGA core array are small,

efficient and can implement any pair of Boolean functions of (the same) three inputs or any

single Boolean function of four inputs. The cell’s small size leads to arrays with large numbers

of cells. A simple, high-speed busing network provides fast, efficient communication over

medium and long distances.

The Symmetrical

Array

At the heart of the Atmel FPSLIC architecture is a symmetrical array of identical cells. The

array is continuous from one edge to the other, except for bus repeaters spaced every four

cells, see Figure 3. At the intersection of each repeater row and column is a 32 x 4 RAM block

accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-

ported RAM, with either synchronous or asynchronous operation.

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