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DAC3550A Datasheet(PDF) 5 Page - Micronas |
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DAC3550A Datasheet(HTML) 5 Page - Micronas |
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5 / 35 page  DAC 3550A Micronas 5 2. Functional Description 2.1. I2S Interface The I2S interface is the digital audio interface between the DAC 3550A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It cov- ers most of the I2S-compatible formats. All modes have two common features: 1. The MSB is left justified to an I2S frame identifica- tion (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode In this case, the bit clock is 32 × fs audio. Maximum word length is 16 bit. 32-bit mode In this case, the bit clock is 64 × fs audio. Maximum word length is 32 bit. Automatic Detection No I2C control is required to switch between 16- and 32-bit mode. It is recommended to switch the DAC 3550A into mute position during changing between 16- and 32-bit mode. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available). Left-Right Selection Standard I2S format defines an audio frame always starting with left channel and low-state of WSI. How- ever, I2C control allows changing the polarity of WSI. Delay Bit Standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I2Ccontrol. Fig. 2–1: I2S 16-bit mode (LR_SEL=0) Fig. 2–2: I2S 32-bit mode (LR_SEL=0) Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks. CLI DAI Vh Vl WSI left 16-bit audio sample right 16-bit audio sample 15 14 13 12 11 10 98 76543210 13 12 11 10 9 8 76543210 15 14 Vh Vl Vh Vl programmable delay bit CLI DAI Vh Vl WSI left 32-bit audio sample right 32-bit audio sample 29 28 27 26 25 24 76543210 31 30 Vh Vl Vh Vl programmable delay bit 29 28 27 26 25 24 76543210 31 30 |
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