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SLK2501IPZPG4 Datasheet(PDF) 5 Page - Texas Instruments |
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SLK2501IPZPG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 22 page www.ti.com SLK2501 SLLS502C – OCTOBER 2001 – REVISED MARCH 2007 TERMINAL FUNCTIONS (continued) TERMINAL TYPE DESCRIPTION NAME NO. PS 21 TTL input (with Polarity select. This pin, used with the SIGDET pin, sets the polarity of SIGSET. When pulldown) high, SIGDET is an active low signal. When low, SIGDET is an active high signal. RX_MONITOR 47 TTL input (with RX parallel data monitor in repeater mode. This pin is only used when the device is put pulldown) under repeater mode. When high, the RX demultiplexer circuit is enabled and the parallel data is presented. When low, the demultiplexer is shut down to save power. LCKREFN 24 TTL input (with Lock to reference. When this pin is low, RXCLKP/N output is forced to lock to REFCLK. pullup) When high, RXCLKP/N is the divided down clock extracted from the receive serial data. LOOPTIME 51 TTL input (with Loop timing mode. When this pin is high, the PLL for the clock synthesizer is bypassed. pulldown) The recovered clock timing is used to send the transmit data. TESTEN 43 TTL input (with Production test mode enable. This pin must be left unconnected or tied low. pulldown) RATEOUT0 37 TTL output Autorate detection outputs. When AUTO_DETECT is high, the autodetection circuit RATEOUT1 36 generates these two bits to indicate the data rates for the downstream device. LOL 45 TTL output Loss of lock. When the clock recovery loop has locked to the input data stream and the phase differs by less than 100 ppm from REFCLK, then LOL is high. When the phase of the input data stream differs by more than 100 ppm from REFCLK, then LOL is low. If the difference is too large (> 500 ppm), the LOL output is not valid. LOS 46 TTL output Loss of signal. When no transitions appear on the input data stream for more than 2.3 µs, a loss of signal occurs and LOS goes high. The device also transmits all zeroes downstream using REFCLK as its clock source. When a valid SONET signal is received, the LOS signal goes low. PRBSPASS 42 TTL output PRBS test result. This pin reports the status of the PRBS test results (high = pass). When PRBSEN is disabled, the PRBSPASS pin is set low. When PRBSEN is enabled and a valid PRBS is received, then the PRBSPASS pin is set high. PAR_VALID 2 TTL output Parity checker output. The internal parity checker on the parallel side of the transmitter checks for even parity. If there is a parity error, the pin is pulsed low for two clock cycles. SPILL 49 TTL output TX FIFO collision output VOLTAGE SUPPLY AND RESERVED PINS VDDLVDS 62, 72, 75, Supply LVDS supply voltage (2.5 V) 78, 90–92, 97 GNDLVDS 61, 69, 76, Ground LVDS ground 77, 89, 93, 96, 100 VDD 3, 22, 25, Supply Digital logic supply voltage (2.5 V) 29, 32, 35, 50 GND 1, 6, 19, Ground Digital logic ground 23, 26, 28, 30, 31, 33, 40 VDDA 7, 16 Supply Analog voltage supply (2.5 V) GNDA 10, 13 Ground Analog ground VDDPLL 11 Supply PLL voltage supply (2.5 V) GNDPLL 12 Supply PLL ground RSVD 52 Reserved This pin needs to be tied to ground or left floating for normal operation. 5 Submit Documentation Feedback |
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