LM2506 datasheet(6/25 Pages) TI1

6 / 25 page

PCLK

PDOUT*

tPZXclk

PCLK

PDOUT*

tPXZclk

SLV

Outputs

80%

20%

VDDIO

0V

tRISE

tFALL

tDVBC

tDVAC

tDVBC

tDVAC

MC

MDn

LM2506

SNLS186B – AUGUST 2006 – REVISED MAY 2013

www.ti.com

TIMING DIAGRAMS

Figure 1. Serial Data Valid—DES Input Set and Hold Time

Figure 2. DES Output Rise and Fall Time (PCLK)

Figure 3. Stop Clock Power Down (SER)

Figure 4. Stop Clock Power Up (SER)

6

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