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SCANSTA111SMX Datasheet(PDF) 1 Page - Texas Instruments |
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SCANSTA111SMX Datasheet(HTML) 1 Page - Texas Instruments |
1 / 38 page SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port Check for Samples: SCANSTA111 1 FEATURES DESCRIPTION The SCANSTA111 extends the IEEE Std. 1149.1 test 2 • True IEEE 1149.1 Hierarchical and Multidrop bus into a multidrop test bus environment. The Addressable Capability advantage of a multidrop approach over a single • The 7 Slot Inputs Support Up to 121 Unique serial scan chain is improved test throughput and the Addresses, an Interrogation Address, ability to remove a board from the system and retain Broadcast Address, and 4 Multi-Cast Group test access to the remaining modules. Each Addresses (Address 000000 is Reserved) SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or • 3 IEEE 1149.1-Compatible Configurable Local combined serially. Addressing is accomplished by Scan Ports loading the instruction register with a value matching • Mode Register0 Allows Local TAPs to be that of the Slot inputs. Backplane and inter-board Bypassed, Selected for Insertion Into the Scan testing can easily be accomplished by parking the Chain Individually, or Serially in Groups of local TAP Controllers in one of the stable TAP Two or Three Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be • Transparent Mode can be Enabled with a performed on one port while other scan chains are Single Instruction to Conveniently Buffer the simultaneously tested. Backplane IEEE 1149.1 Pins to those on a Single Local Scan Port • LSP ACTIVE Outputs Provide Local Port Enable Signals for Analog Busses Supporting IEEE 1149.4. • General Purpose Local Port Pass-Through Bits are Useful for Delivering Write Pulses for FPGA Programming or Monitoring Device Status. • Known Power-Up State • TRST on All Local Scan Ports • 32-Bit TCK Counter • 16-Bit LFSR Signature Compactor • Local TAPs can become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP0-2 Have a TRI- STATE Notification Output) • 3.0-3.6V VCC Supply Operation • Power-Off High Impedance Inputs and Outputs • Supports Live Insertion/Withdrawal 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2001–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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