TMS370Cx9x

8-BIT MICROCONTROLLER

SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997

4

POST OFFICE BOX 1443

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx9x devices.

Table 1. Memory Configurations

DEVICE

PROGRAM

MEMORY

(BYTES)

DATA MEMORY

(BYTES)

PACKAGES

44 PIN PLCC/CLCC, OR

40 PIN PSDIP/CSDIP

ROM

EPROM

RAM

EEPROM

40 PIN PSDIP/CSDIP

TMS370C090A

4K

—

128

256

FN – PLCC / NJ‡ – PSDIP

TMS370C792

—

8K

128

256

FN – PLCC / NJ‡ – PSDIP

SE370C792†

—

8K

128

256

FZ – CLCC / JC – CSDIP

† System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

‡ The NJ designator for the 40-pin plastic shrink DIP package was formerly known as N2. The mechanical drawing of the NJ is identical to the N2

package and did not need to be requalified.

The suffix letter A appended to the device names shown in the device column of Table 1 indicates the

configuration of the device. ROM and EPROM devices have a different configuration as indicated in Table 2.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE§

WATCHDOG TIMER

CLOCK

LOW-POWER MODE

EPROM without A

Standard

Divide by 4 (Standard oscillator)

Enabled

EPROM without A

Standard

Divide-by-4 (Standard oscillator)

Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

Simple

§ Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

The 4K bytes of mask-programmable ROM in the associated TMS370Cx9x device are replaced with 8K bytes

of EPROM in the TMS370C792 while all other available memory and on-chip peripherals are identical. A

one-time-programmable device (OTP) (TMS370C792) and a reprogrammable device (SE370C792) are

available.

The TMS370C792 OTP device is available in a plastic package. This microcontroller is effective for use as an

immediate production update for the TMS370Cx9x ROM device or for low-volume production runs when the

mask charge or cycle time for the low-cost mask-ROM device is not practical.

The SE370C792 has a windowed ceramic package that allows reprogramming of the program EPROM memory

during the development / prototyping design phase. The SE370C792 device allows quick updates to

breadboards and prototype systems while iterating initial designs.

The TMS370Cx9x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In

the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode,

all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

The TMS370Cx9x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx9x family is fully

instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller

family.