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ADUC7027AST62 Datasheet(PDF) 10 Page - Analog Devices |
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ADUC7027AST62 Datasheet(HTML) 10 Page - Analog Devices |
10 / 80 page ADuC702x Series Preliminary Technical Data Rev. PrB | Page 10 of 80 PIN FUNCTION DESCRIPTIONS – ADUC7020/ADUC7021/ADUC7022 Table 3. Pin Function Descriptions Pin# ADuC702X 7020 7021 7022 Mnemonic Type* Function 38 37 36 ADC0 I Single-ended or differential Analog input 0 39 38 37 ADC1 I Single-ended or differential Analog input 1 40 39 38 ADC2/CMP0 I Single-ended or differential Analog input 2 / Comparator Positive Input 1 40 39 ADC3/CMP1 I Single-ended or differential Analog input 3 / Comparator Negative Input 2 1 40 ADC4 I Single-ended or differential Analog input 4 - 2 1 ADC5 I Single-ended or differential Analog input 5 - 3 2 ADC6 I Single-ended or differential Analog input 6 - 4 3 ADC7 I Single-ended or differential Analog input 7 - - 4 ADC8 I Single-ended or differential Analog input 8 - - 5 ADC9 I Single-ended or differential Analog input 9 3 5 6 GNDREF S Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND 4 6 - DAC0/ADC12 I/O DAC0 Voltage Output / Single-ended or differential Analog input 12 5 7 - DAC1/ADC13 I/O DAC1 Voltage Output / Single-ended or differential Analog input 13 6 - - DAC2/ADC14 I/O DAC2 Voltage Output / Single-ended or differential Analog input 14 7 - - DAC3/ADC15 I/O DAC3 Voltage Output / Single-ended or differential Analog input 15 8 8 7 TMS I JTAG Test Port Input - Test Mode Select. Debug and download access 9 9 8 TDI I JTAG Test Port Input – Test Data In. Debug and download access 10 10 9 BM/P0.0/CMPOUT/P LAI[7] I/O Multifunction I/O pin: Boot Mode. The ADuC702X will enter serial download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage Comparator Output/ Programmable Logic Array Input Element 7 11 11 10 P0.6/T1/MRST/PLA O[3] O Multifunction pin: driven low after reset General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output / Programmable Logic Array Output Element 3 12 12 11 TCK I JTAG Test Port Input - Test Clock. Debug and download access 13 13 12 TDO O JTAG Test Port Output - Test Data Out. Debug and download access 14 14 13 IOGND S Ground for GPIO. Typically connected to DGND 15 15 14 IOVDD S 3.3V Supply for GPIO and input of the on-chip voltage regulator. 16 16 15 LVDD S 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47 µF capacitor to DGND 17 17 16 DGND S Ground for core logic. 18 18 17 P0.3/TRST/ADCBUSY I General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test Reset. Debug and download access / ADCBUSY signal output 19 19 18 RST I Reset Input. (active low) 20 20 19 IRQ0/P0.4/CONVST ART /PLAO[1] I/O Multifunction I/O pin: External Interrupt Request 0, active high / General Purpose Input-Output Port 0.4 / Start conversion input signal for ADC / Programmable Logic Array Output Element 1 21 21 20 IRQ1/P0.5/ADCBUSY /PLAO[2] I/O Multifunction I/O pin: External Interrupt Request 1, active high / General Purpose Input-Output Port 0.5 / ADCBUSY signal / Programmable Logic Array Output Element 2 22 22 21 P2.0/SPM9/PLAO[ 5]/CONVSTART I/O Serial Port Multiplexed: General Purpose Input-Output Port 2.0 / UART / Programmable Logic Array Output Element 5/ Start conversion input signal for ADC 23 23 22 P0.7/ECLK/SPM8/ PLAO[4]/XCLK I/O Serial Port Multiplexed: General Purpose Input-Output Port 0.7 / Output for External Clock signal / UART / Programmable Logic Array Output Element 4/ Input to the |
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