1

16

7

6

5

4

3

2

10

11

12

13

14

15

DAP

(GND)

SCLK

SDO

DGND

CFB

VDD

CLDO

XOUT

INB

GND

TBCLK/XIN

INTB

8

9

CSB

SDI

VIO

CFA

INA

LDC1000

SNOSCX2C – SEPTEMBER 2013 – REVISED SEPTEMBER 2015

www.ti.com

5 Pin Configuration and Functions

NHR Package

16-Pin WSON

Top View

Pin Functions

PIN

DESCRIPTION

NAME

NO.

SCLK

1

DI

SPI clock input. SCLK is used to clock-out/clock-in the data from/into the chip

CSB

2

DI

SPI CSB. Multiple devices can be connected on the same SPI bus with each device having a

dedicated CSB connection to the MCU so that each device can be uniquely selected.

SDI

3

DI

SPI Slave Data In (Master Out Slave In). This should be connected to the Master Out Slave In of the

master

VIO

4

P

Digital IO Supply

DGND

6

P

Digital ground

SDO

5

DO

SPI Slave Data Out (Master In Slave Out).It is Hi-Z when CSB is high

CFB

7

A

LDC filter capacitor

CFA

8

A

LDC filter capacitor

INA

9

A

External LC Tank. Connected to external LC tank

INB

10

A

External LC Tank. Connected to external LC tank

GND

11

P

Analog ground

VDD

12

P

Analog supply

CLDO

13

A

LDO bypass capacitor. A 56 nF capacitor should be connected from this pin to GND

TBCLK/XI

14

DI/A

External time-base clock/XTAL. Either an external clock or crystal can be connected.

N

XOUT

15

A

XTAL. Crystal out. When using a crystal, a crystal should be connected across XIN and XOUT. When

not using a crystal, this pin should be left floating.

INTB

16

DO

Configurable interrupt output.

DAP

17

P

(1)

DO: Digital Output, DI: Digital Input, P: Power, A: Analog

(2)

There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the GND pin of the device. Although the DAP

can be left floating, for best performance the DAP should be connected to the same potential as the devices's GND pin. Do no use the

DAP as the primary ground for the device. The device GND pin must always be connected to ground.

4

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