DS92LV2421 datasheet(7/59 Pages) TI1

Part #	DS92LV2421

Description	10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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Manufacturer	TI1 [Texas Instruments]

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DS92LV2421, DS92LV2422

www.ti.com

SNLS321C – MAY 2010 – REVISED MAY 2016

Product Folder Links: DS92LV2421 DS92LV2422

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(1)

G = Ground, I = Input, O = Output, and P = Power

(2)

1= HIGH, 0 = LOW

(3)

For a high state, use a 10-k

Ω pullup to VDDIO; for a low state, the IO includes an internal pull down. The strap pins are read upon power-

up and set device configuration. Pin number DO[23:0] listed along with shared data output name in square brackets.

Table 1. Pin Functions: DS92LV2422 (Deserializer)

TYPE(1)

DESCRIPTION(2)

NAME

NO.

LVCMOS PARALLEL INTERFACE

DO[7:0]

33, 34, 35,

36, 37, 39,

40, 41

I/O

Parallel interface data output pins, STRAP and LVCMOS.

For 8-bit RED display: DO7 = R7 – MSB, DO0 = R0 – LSB.

In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins

are inputs during power-up (see Deserializer Strap Input Pins).

DO[15:8]

20, 21, 22,

23, 25, 26,

27, 28

I/O

Parallel interface data output pins, STRAP and LVCMOS.

For 8-bit GREEN display: DO15 = G7 – MSB, DO8 = G0 – LSB.

In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins

are inputs during power-up (see Deserializer Strap Input Pins).

DO[23:16]

9, 10, 11,

12, 14, 17,

18, 19

I/O

Parallel interface data input pins, STRAP and LVCMOS.

For 8-bit BLUE display: DO23 = B7 – MSB, DO16 = B0 – LSB.

In power down (PDB = 0), outputs are controlled by the OSS_SEL (see Table 7). These pins

are inputs during power-up (see Deserializer Strap Input Pins).

CO1

6

O

Control signal output, LVCMOS.

For display or video application: CO1 = Data enable output.

Control signal pulse width must be 3 clocks or longer to be transmitted when the control

signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the control signal filter is disabled (CONFIG[1:0] = 00).

The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter

setting.

In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7).

CO2

8

O

Control signal output, LVCMOS.

For display or video application: CO2 = Horizontal sync output.

Control signal pulse width must be 3 clocks or longer to be transmitted when the control

signal filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the control signal filter is disabled (CONFIG[1:0] = 00).

The signal is limited to 2 transitions per 130 clocks regardless of the control signal filter

setting.

In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7).

CO3

7

O

Control signal output, LVCMOS.

For display or video application: CO3 = Vertical sync output.

CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.

Thus, the minimum pulse width allowed is 130 clock cycles wide.

The CONFIG[1:0] pins have no effect on the CO3 signal.

In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7).

CLKOUT

5

O

Pixel clock output, LVCMOS.

In power down (PDB = 0), output is controlled by the OSS_SEL pin (see Table 7). Data strobe

edge set by RFB.

LOCK

32

O

LOCK status output, LVCMOS.

LOCK = 1, PLL is locked, outputs are active

LOCK = 0, PLL is unlocked, DO[23:0], CO1, CO2, CO3 and CLKOUT output states are

controlled by OSS_SEL (see Table 7).

May be used as link status or to flag when video data is active (ON/OFF).

PASS

42

O

PASS output (BIST mode), LVCMOS.

PASS = 1, error free transmission.

PASS = 0, one or more errors were detected in the received payload.

Route to test point for monitoring, or leave open if unused.

CONTROL AND CONFIGURATION – STRAP PINS(3)

CONFIG[1:0]

10 [DO22],

9 [DO23]

I

STRAP or LVCMOS with pulldown.

00: Control Signal Filter DISABLED.

01: Control Signal Filter ENABLED.

10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241-Q1.

11: Reverse compatibility mode to interface with the DS90C241.

LF_MODE

12 [DO20]

I

SSCG low frequency mode, STRAP or LVCMOS with pulldown.

Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE (X).

LF_MODE = 1, SSCG in low frequency mode (CLK = 10 to 20 MHz).

LF_MODE = 0, SSCG in high frequency mode (CLK = 20 to 65 MHz).

This can also be controlled by I2C register access.

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