DS92LV2411 datasheet(6/54 Pages) TI1

Part #	DS92LV2411

Description	5 to 50 MHz 24-Bit Channel Link II Serializer And Deserializer

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Manufacturer	TI1 [Texas Instruments]

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DS92LV2412

TOP VIEW

DAP = GND

NC

PDB

VDDPR

ID[x]

ROUT-

ROUT+

RIN-

RIN+

NC

DO18/OSS_SEL

DO16

DO15/EQ3

DO12/EQ0

VDDIO

DO10/OSC_SEL2

DO9/OSC_SEL1

CMF

VDDCMLO

VDDR

VDDSC

DO17/RFB

DO14/EQ2

DO13/EQ1

DO11

30

29

28

VDDL

NC

DO8/OSC_SEL0

46

47

48

RES

NC

VDDIR

BOLD PIN NAME ± indicates I/O strap

pin associated with output pin

49

DS92LV2411, DS92LV2412

SNLS302E – MAY 2010 – REVISED FEBRUARY 2015

www.ti.com

60-Pin WQFN

Package NKB

Top View

Pin Functions, DS92LV2412 Deserializer (1)

TYPE

DESCRIPTION

NAME

NO.

LVCMOS PARALLEL INTERFACE

CLKOUT

5

O, LVCMOS

Pixel Clock Output

In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6). Data

strobe edge set by RFB.

CO1

6

O, LVCMOS

Control Signal Output

For Display/Video Application:

CO1 = Data Enable Output

Control signal pulse width must be 3 clocks or longer to be transmitted when the Control

Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).

The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter

setting.

In power-down (PDB = 0), output is controlled by the OSS_SEL Pin (See Table 6).

(1)

NOTE: 1 = HIGH, 0 = LOW

The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on

the PDB Pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.

6

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