DS92LV1021, DS92LV1210

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SNLS024C – MARCH 1999 – REVISED APRIL 2013

Deserializer Switching Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Max

Units

Deserializer PLL Lock

16MHz

7

15

μs

Time from PWRDWN

See Figure 14

40MHz

4.8

25.6

μs

(with SYNCPAT)

See Figure 15

Deserializer PLL Lock

16MHz

7

10

μs

time from SYNCPAT

40MHz

4.5

7

μs

TRI-STATE to HIGH

LOCK

1.5

12

ns

Delay (power-up)

Deserializer Noise

See Figure 16

16 MHz

400

1100

ps

Margin

40 MHz

100

400

ps

(2)

For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and

specific conditions of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1

timing or tDSR2 timing. tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down

mode. Synchronization patterns should be sent to the device before initiating either condition. tDSR2 is the time required to indicate lock

for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving

synchronization patterns (SYNCPATs).

(3)

tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.

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