DS92LV0412 datasheet(5/53 Pages) TI1

Part #	DS92LV0412

Description	5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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Manufacturer	TI1 [Texas Instruments]

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DS92LV0411, DS92LV0412

www.ti.com

SNLS331B – MAY 2010 – REVISED APRIL 2013

Table 1. DS92LV0411 PIN DESCRIPTIONS

Pin Name

Pin #

I/O, Type

Description

Channel Link Parallel Input Interface

RxIN[3:0]+

2, 33, 31,

I, LVDS

True LVDS Data Input

29

These inputs require an external 100

Ω differential termination for standard LVDS levels.

RxIN[3:0]-

1, 34, 32,

I, LVDS

Inverting LVDS Data Input

30, 28

These inputs require an external 100

Ω differential termination for standard LVDS levels.

RxCLKIN+

35

I, LVDS

True LVDS Clock Input

These inputs require an external 100

Ω differential termination for standard LVDS levels.

RxCLKIN-

34

I, LVDS

Inverting LVDS Clock Input

These inputs require an external 100

Ω differential termination for standard LVDS levels.

Control and Configuration

PDB

23

I, LVCMOS

Power-down Mode Input

w/ pull-down

PDB = 1, Device is enabled (normal operation).

Refer to POWER UP REQUIREMENTS AND PDB PIN in the Applications Information

Section.

PDB = 0, Device is powered down

When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high,

the PLL is shutdown, IDD is minimized. Control Registers are RESET.

VODSEL

20

I, LVCMOS

Differential Driver Output Voltage Select — Pin or Register Control

w/ pull-down

VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications

VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)

De-Emph

19

I, Analog

De-Emphasis Control — Pin or Register Control

w/ pull-up

De-Emph = open (float) - disabled

To enable De-emphasis, tie a resistor from this pin to GND or control via register.

(See Table 5)

MAPSEL

26

I, LVCMOS

Channel Link Map Select — Pin or Register Control

w/ pull-down

MAPSEL = 1, MSB on RxIN3+/-. (SeeFigure 23)

MAPSEL = 0, LSB on RxIN3+/-. (See Figure 22)

CONFIG[1:0]

10, 9

I, LVCMOS

Operating Modes

w/ pull-down

Determines the device operating mode and interfacing device. (See Table 2)

CONFIG[1:0] = 00: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter

DISABLED

CONFIG[1:0] = 01: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter

ENABLED

CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124

CONFIG [1:0] = 11: Interfacing to DS90C124

ID[x]

4

I, Analog

Serial Control Bus Device ID Address Select — Optional

Resistor to Ground and 10 k

Ω pull-up to 1.8V rail. (See Table 11)

SCL

6

I, LVCMOS

Serial Control Bus Clock Input - Optional

SCL requires an external pull-up resistor to 3.3V

SDA

7

I/O, LVCMOS Serial Control Bus Data Input / Output - Optional

Open Drain

SDA requires an external pull-up resistor to 3.3V

BISTEN

21

I, LVCMOS

BIST Mode — Optional

w/ pull-down

BISTEN = 1, BIST is enabled

BISTEN = 0, BIST is disabled

RES[7:0]

25, 3, 36,

I, LVCMOS

Reserved - tie LOW

27, 18, 13,

w/ pull-down

12, 8

Channel Link II Serial Interface

DOUT+

16

O, CML

True Output.

The output must be AC Coupled with a 0.1

μF capacitor.

DOUT-

15

O, CML

Inverting Output.

The output must be AC Coupled with a 0.1

μF capacitor.

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