DS92LV010A

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SNLS007E – MAY 1998 – REVISED APRIL 2013

DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver

Check for Samples: DS92LV010A

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FEATURES

DESCRIPTION

The DS92LV010A is one in a series of transceivers

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•

Bus LVDS Signaling (BLVDS)

designed specifically for the high speed, low power

•

Designed for Double Termination Applications

proprietary bus backplane interfaces. The device

•

Balanced Output Impedance

operates from a single 3.3V or 5.0V power supply

and includes one differential line driver and one

•

Lite Bus Loading 5pF Typical

receiver. To minimize bus loading the driver outputs

•

Glitch Free Power Up/Down (Driver Disabled)

and receiver inputs are internally connected. The

•

3.3V or 5.0V Operation

logic interface provides maximum flexibility as 4

separate lines are provided (DIN, DE, RE, and

•

±1V Common Mode Range

ROUT). The device also features flow through which

•

±100mV Receiver Sensitivity

allows easy PCB routing for short stubs between the

•

High Signaling Rate Capability (Above 100

bus pins and the connector. The driver has 10 mA

Mbps)

drive capability, allowing it to drive heavily loaded

backplanes, with impedance as low as 27 Ohms.

•

Low Power CMOS Design

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Product Offered in 8 Lead SOIC Package

The driver translates between TTL levels (single-

ended) to Low Voltage Differential Signaling levels.

•

Industrial Temperature Range Operation

This

allows

for

high

speed

operation,

while

consuming minimal power with reduced EMI. In

addition the differential signaling provides common

mode noise rejection of ±1V.

The receiver threshold is ±100mV over a ±1V

common mode range and translates the low voltage

differential levels to standard (CMOS/TTL) levels.

CONNECTION DIAGRAM

Figure 1. SOIC Package

See Package Number D0008A

BLOCK DIAGRAM

Figure 2.

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PRODUCTION DATA information is current as of publication date.

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Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.