NRND

DS90LV049H

SNLS200A – SEPTEMBER 2005 – REVISED APRIL 2013

www.ti.com

APPLICATION INFORMATION

General application guidelines and hints for LVDS drivers and receivers may be found in the following application

notes: LVDS Owner's Manual (lit #550062-003), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165),

AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 10. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media

is in the range of 100

Ω. A termination resistor of 100 Ω (selected to match the media), and is located as close to

the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into

a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver

configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as

well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The TRI-STATE function allows the device outputs to be disabled, thus obtaining an even lower power state

when the transmission of data is not required.

The DS90LV049H has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of

the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and

the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise

isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1

μF and 0.001 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple

vias should be used to connect the decoupling capacitors to the power planes. A 10

μF (35 V) or greater solid

tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply

and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL

and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differential impedance of your transmission medium (that is,

cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they

leave the IC (stubs should be < 10 mm long). This will help eliminate reflections and ensure noise is coupled as

common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than

traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise

induced on the differential lines is much more likely to appear as common-mode which is rejected by the

receiver.

Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase

difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI

will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118

in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match

differential impedance and provide isolation for the differential lines. Minimize the number or vias and other

discontinuities on the line.

Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.

Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode

rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid

discontinuities in differential impedance. Minor violations at connection points are allowable.

10

Submit Documentation Feedback

Copyright © 2005–2013, Texas Instruments Incorporated

Product Folder Links: DS90LV049H