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DS90LT012AQ-Q1 Datasheet(PDF) 6 Page - Texas Instruments |
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DS90LT012AQ-Q1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 14 page DS90LT012AQ SNLS297E – MAY 2008 – REVISED APRIL 2013 www.ti.com Figure 6. VTC of the DS90LT012AQ LVDS Receiver FAIL SAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5k Ω to 15kΩ range to minimize loading and waveform distortion to the driver. The common- mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194 (SNLA051), “Failsafe Biasing of LVDS Interfaces” for more information. PROBING LVDS TRANSMISSION LINES Always use high impedance (> 100k Ω), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS When choosing cable and connectors for LVDS it is important to remember: Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100 Ω. They should not introduce major impedance discontinuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and relatively inexpensive. PIN DESCRIPTIONS Package Pin Number Pin Name Description SOT-23 4 IN − Inverting receiver input pin 3 IN+ Non-inverting receiver input pin 5 TTL OUT Receiver output pin 1 VDD Power supply pin, +3.3V ± 0.3V 2 GND Ground pin 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: DS90LT012AQ |
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