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DS90CR486 Datasheet(PDF) 1 Page - Texas Instruments |
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DS90CR486 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 22 page DS90CR486 www.ti.com SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013 DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps) Check for Samples: DS90CR486 The DS90CR486 deserializer is improved over prior 1 FEATURES generations of Channel Link devices and offers 2 • Up to 6.384 Gbps Throughput higher bandwidth support and longer cable drive with • 66MHz to 133MHz Input Clock Support three areas of enhancement. To increase bandwidth, the maximum clock rate is increased to 133 MHz and • Reduces Cable and Connector Size and Cost 8 serialized LVDS outputs are provided. Cable drive • Cable Deskew Function is enhanced with a user selectable pre-emphasis (on • DC Balance Reduces ISI Distortion DS90CR485) feature that provides additional output current during transitions to counteract cable loading • For Point-to-Point Backplane or Cable effects. Optional DC balancing on a cycle-to-cycle Applications basis, is also provided to reduce ISI (Inter-Symbol • Low Power, 890 mW Typ at 133MHz Interference). With pre-emphasis and DC balancing, • Flow through Pinout for Easy PCB Design a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been • +3.3V Supply Voltage added to deskew long cables of pair-to-pair skew. • 100-pin TQFP Package These three enhancements allow long cables to be • Conforms to TIA/EIA-644-A-2001 LVDS driven. Standard The DS90CR486 is intended to be used with the DS90CR485 Channel Link Serializer. It is also DESCRIPTION backward compatible with serializers DS90CR481 The DS90CR486 receiver converts eight Low Voltage and DS90CR483. The DS90CR486 is footprint Differential Signaling (LVDS) data streams back into compatible with the DS90CR484. 48 bits of LVCMOS/LVTTL data. Using a 133MHz The chipset is an ideal solution to solve EMI and clock, the data throughput is 6.384Gbit/s interconnect size problems for high-throughput point- (798Mbytes/s). to-point applications. The multiplexing of data lines provides a substantial For more details, please refer to the APPLICATIONS cable reduction. Long distance parallel single-ended INFORMATION section of this datasheet. buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in interconnect width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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Similar Description - DS90CR486_15 |
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