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DP83910A Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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DP83910A Datasheet(HTML) 2 Page - National Semiconductor (TI) |
2 / 12 page 20 Block Diagram TLF9365 – 2 30 Functional Description The DP83910A consists of five main logical blocks a) The oscillator generates the 10 MHz transmit clock signal for system timing b) The Manchester encoder accepts NRZ data from the controller encodes the data to Manchester and trans- mits it differentially to the transceiver through the differ- ential transmit driver c) The Manchester decoder receives Manchester data from the transceiver converts it to NRZ data and clock pulses and sends it to the controller d) The collision translator indicates to the controller the presence of a valid 10 MHz collision signal to the PLL e) The loopback circuitry when asserted routes the data from the Manchester encoder back to the PLL decoder 31 OSCILLATOR The oscillator is controlled by a 20 MHz parallel resonant crystal connected between X1 and X2 or by an external clock on X1 The 20 MHz output of the oscillator is divided by 2 to generate the 10 MHz transmit clock for the control- ler The oscillator also provides internal clock signals to the encoding and decoding circuits If a crystal is connected to the DP83910A it is recommend- ed that the circuit shown in Figure 1 be used and that the components used meet the following Crystal XT1 AT cut parallel resonant crystal Series Resistance s10X Specified Load Capacitance 135 pF Accuracy 0005% (50 ppm) C1 C2 Load Capacitor 27 pF The resistor R1 in Figure 1 may be required in order to minimize frequency drift due to changes in the VCC supply voltage If R1 is required it’s value must be carefully select- ed R1 decreases the loop gain Thus if R1 is made too large the loop gain will be greatly reduced and the crystal will not oscillate If R1 is made too small normal variations in the VCC may cause the oscillation frequency to drift out of specification As the first rule of thumb the value of R1 TLF9365 – 15 Note 1 The resistor R1 may be required in order to minimize frequency drift due to changes in the VCC See text description FIGURE 1 Crystal Connection to DP83910A (see text for component values) should be made equal to five times the motional resistance of the crystal The motional resistance of 20 MHz crystals is usually in the range of 10X to 30X This implies that a reasonable value for R1 should be in the range of 50X – 150X The decision of whether or not to include R1 should be based upon measured variations of crystal frequency as each of the circuit parameters is varied According to the IEEE 8023 standard the entire oscillator circuit (crytsal and amplifier) must be accurate to 001% When using a crystal the X1 pin is not guaranteed to pro- vide a TTL compatible logic output and should not be used to drive external standard logic If additional logic needs to be driven then an external oscillator should be used as described in the following 32 OSCILLATOR MODULE OPERATION If the designer wishes to use a crystal clock oscillator one that provides the following should be employed 1) TTL or CMOS output with a 001% frequency tolerance 2) 40% – 60% duty cycle 3) t2 TTL load output drive (IOL e 32 mA) 2 |
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