DS90C365A

www.ti.com

SNLS181I – APRIL 2004 – REVISED APRIL 2013

+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

Check for Samples: DS90C365A

1

FEATURES

DESCRIPTION

The

DS90C365A

is

a

pin

to

pin

compatible

23

•

Pin-to-pin compatible to DS90C363,

replacement

for

DS90C363,

DS90C363A

and

DS90C363A and DS90C365

DS90C365. The DS90C365A has additional features

•

No special start-up sequence required

and improvements making it an ideal replacement for

between clock/data and /PD pins. Input signals

DS90C363, DS90C363A and DS90C365. family of

(clock and data) can be applied either before

LVDS Transmitters.

or after the device is powered.

The DS90C365A transmitter converts 21 bits of

•

Support Spread Spectrum Clocking up to

LVCMOS/LVTTL data into four LVDS (Low Voltage

100kHz frequency modulation & deviations of

Differential Signaling) data streams. A phase-locked

±2.5% center spread or -5% down spread.

transmit clock is transmitted in parallel with the data

streams over the fourth LVDS link. Every cycle of the

•

“Input Clock Detection” feature will pull all

transmit clock 21 bits RGB of input data are sampled

LVDS pairs to logic low when input clock is

and transmitted. At a transmit clock frequency of 87.5

missing and when /PD pin is logic high.

MHz, 21 bits of RGB data and 3 bits of LCD timing

•

18 to 87.5 MHz shift clock support

and control data (FPLINE, FPFRAME, DRDY) are

•

Tx power consumption < 146 mW (typ) at 87.5

transmitted at a rate of 612.5 Mbps per LVDS data

channel. Using a 87.5 MHz clock, the data throughput

MHz Grayscale

is 229.687 Mbytes/sec. This transmitter can be

•

Tx Power-down mode < 37 uW (typ)

programmed for Rising edge strobe or Falling edge

•

Supports VGA, SVGA, XGA, SXGA (dual pixel),

strobe through a dedicated pin. A Rising edge or

SXGA+ (dual pixel), UXGA (dual pixel).

Falling edge strobe transmitter will interoperate with a

Falling edge strobe FPDLink Receiver without any

•

Narrow bus reduces cable size and cost

translation logic.

•

Up to 1.785 Gbps throughput

This chipset is an ideal means to solve EMI and

•

Up to 223.125 Megabytes/sec bandwidth

cable size problems associated with wide, high-speed

•

345 mV (typ) swing LVDS devices for low EMI

TTL interfaces with added Spead Spectrum Clocking

•

PLL requires no external components

support..

•

Compliant to TIA/EIA-644 LVDS standard

•

Low profile 48-lead TSSOP package

Block Diagram

1

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PRODUCTION DATA information is current as of publication date.

Copyright © 2004–2013, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.